Analog Macro-Cell Placement with Very Fast Simulated Re-Annealing Algorithm

This paper presents the analog macro-cell placement using the novel very fast simulated re-annealing algorithm, which is exponentially faster than the classical Cauchy or Bolzmann annealing. A slide function is applied to convert the absolute placement to relative placement, which greatly decreases the configuration space without degrading the searching opportunity. The cost function is set up deliberately to meet the special requirements of analog integrated circuits. Several net-length estimators are implemented which analog-circuit designers can choose with a trade-off between accuracy and efficiency. The global routing using the minimum Steiner tree is developed, which runs simultaneously during the placement configuration searching. This will ease the successive detail routing and greatly decrease the revise of final placement result. The layout example of optional amplifier is given to demonstrate its usability. The application of this algorithm drastically improves the design efficiency.